Meeting date: 11 apr 2006
Members (asterisk for those attending):
*Arpad Muranyi,
*Bob Ross,
*Todd Westerhoff,
*Mike LaBonte,
*Paul Fernando,
*Barry Katz,
Walter Katz,
Ken Willis,
*Ian Dodd
Lance Wang
*Richard Ward
*Doug White

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Review of ARs:

AR: Richard prepare short presentation on TI design
- Done

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Richard Ward presentation

- Presentation ward_serdes_20060411.pdf emailed to reflector.
  - "Serdes Introduction and options for Macro-modelling"
  - uploaded to http://www.eda.org/pub/ibis/macromodel_wip/

- There are many standards for SerDes protocols.
  - Some DC-coupled, some AC.
  - Some Power-referenced, some ground.

- Example eye diagrams:
  - At 3.126GHz the eye looks pretty good even without EQ.
  - At 6.25GHz there is no eye without EQ.

- "Clock/Data Recovery II" method not suited for macro-model.
  - COntains "secret sauce": leaning toward encrypted AMS delivery.

- Receiver Equalization II predicts ISI from previous data.

- Likely candidates for macro-model implementation:
  - Clocked comparator with slew-based offset.
  - Gain/attenuation
  - Programmable FIR TX

- Unlikely candidates for macro-model implementation:
  - Clock/data recovery or EQ as components
  - Small blocks may be too fine-grain to be useful.

To be or not to be --Arpad

- If only the simpler designs can be macro-modeled, where do we stand?
  - Macros give us SPICE compatibility; do we need it?
  - Additional level of difficulty:
    Need to look at received eye diagrams using recovered clock.

- We could create higher level building blocks like PLLs.
  - Mentor has been able to reuse such blocks, but with some
    tweaking of internals, not totally parameterized.
  - May be difficult to implement in SPICE, but can be done.

- Which AMS language statements can't be translated to a macromodel?
  - Hard to say, but AMS models have MANY lines of code.
  - Coding efficiency of circuit language may be the limiting factor.

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Next meeting: Tuesday 18 apr 2006 12:00pm PT